1. Field of the Invention
This invention relates to methods and apparatus for direct digital frequency synthesis. More particularly this invention relates to methods and apparatus for direct digital frequency synthesis employing interpolation of trigonometric functions of angles between the trigonometric function of known angles.
2. Description of Related Art
As is described in A Technical Tutorial on Digital Signal Synthesis, Analog Devices, Norwood, Mass., 199, pp. 5-9, and shown in FIG. 1a, a direct digital synthesizer in its simplest form is implemented from a precision reference clock 5, an address counter 10, a read only memory (ROM) 15, and a digital-to-converter 20. The digital amplitude information that corresponds to a complete cycle of a sine wave is stored in the ROM 15 as a table of sine functions with the addresses of the ROM 15 acting as the angular values of the sine contents of the table. The address counter 10 steps through and accesses each of the ROM's 15 memory locations and the contents (the equivalent sine amplitude words) are presented to the digital-to-analog converter 20. The digital-to-analog converter 20 generates an output frequency Fout 25 that is an analog sine wave in response to the sequence digital input words from the ROM 15.
The output frequency Fout 25 of this direct implementation is dependent on the frequency of the reference clock Fclk 5 and the number of increments of the angular values of the sine function as stored in the ROM 15. While the analog output fidelity, jitter, and AC performance of this simplistic architecture can be quite good, it lacks tuning flexibility. The output frequency Fout 25 can only be changed by changing the frequency of the reference clock Fclk 5 or by reprogramming the ROM 15. Neither of these options support high-speed output frequency hopping such as used in spread spectrum modulation techniques of wireless radio frequency transmission.
With the introduction of a phase accumulator 35 as shown in FIG. 1b, this architecture becomes a numerically controlled oscillator, which is the core of a highly flexible direct digital synthesis device. The phase accumulator 35 is a variable-modulus counter and phase register is implemented in the circuit before ROM 15, as a replacement for the address counter 10. The input word 30 provides a phase angle increment indicating the number of reference clock Fclk 5 pulses needed to construct the output frequency Fout 25. The phase accumulator 35 provides the phase angle 37 that addresses the ROM 15. The ROM 15 then provides the sine amplitude values 45 for the phase angles indicated by the phase accumulator 35.
Referring now to FIG. 1c to visualize the sine wave oscillation as a vector rotating around a unit circle 50. Each designated point on the unit circle 50 corresponds to the equivalent point on a cycle of a sine waveform. As the vector rotates around the circle 50, it is apparent that a corresponding output sine wave is being generated. One revolution of the vector around the unit circle 50, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator 35 is utilized to provide the equivalent of the vector's linear rotation around the unit circle 50. The contents of the phase accumulator 15 correspond to the points on the cycle of the output sine wave. The number of discrete phase points contained in the unit circle 50 is determined by the resolution of the input control word 30, of the phase accumulator 35. The output of the phase accumulator 35 is linear and cannot directly be used to generate a sine wave or any other waveform except a ramp. Therefore, the ROM 15 acts as a phase-to-amplitude lookup table to convert a truncated version of the phase accumulator's 15 instantaneous output value into the sine wave amplitude information that is presented to the digital-to-analog converter 20.
The phase accumulator 35 is actually a modulus M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by a digital input word 30 that is summed with the counter. The input word 30 forms the phase step size between reference clock updates; it effectively sets how many points to skip around the unit circle. The larger the increment size, the faster the phase accumulator overflows and completes its equivalent of a sine wave cycle. For example, an N=32-bit phase accumulator, an M value of 0000 . . . 0001 (one) would result in the phase accumulator overflowing after 232 reference clock cycles (increments). If the M value is changed to 0111 . . . 1111, the phase accumulator will overflow after only 21 clock cycles, or two reference clock cycles. This control of the jump size constitutes the frequency tuning resolution of the direct digital synthesizer architecture. The relationship of the phase accumulator 35 and the input word 30 form the basic tuning equation for direct digital synthesizer architecture:FOUT=(M(FCLK))/2NWhere:                FOUT=the output frequency of the direct digital synthesizer        M=the binary tuning word        Fclk=the internal reference clock frequency (system clock)        N=The length in bits of the phase accumulatorChanges to the value of M in the direct digital synthesizer architecture result in immediate and phase-continuous changes in the output frequency.        
Referring now to FIG. 1d for a description of a direct digital frequency synthesizer of the prior art. The frequency control word 55 provides the phase increment to the phase accumulator 60 to provide the phase modulus of the reference clock Fclk 57 in the generation of the output frequency. The phase accumulator 60 is the modulus M counter used to increment the sine/cosine generator 65. In the description above the sine-cosine generator 65 is the ROM 15 that provides the amplitudes of the sine and/or cosine of the phase angles provided by the phase accumulator 65. The output amplitudes of the sine/cosine generator 70a and 70b are the inputs to the digital-to-analog converters 75a and 75b which creates the quadrature output sine and cosine signals that are the inputs to the low pass filters 80a and 80b. The low pass filters respectively remove any noise components of the quadrature output sine and cosine signals to form the output signals 90a and 90b. 
As the resolution of the frequency adjustment improves, the frequency control word 55 becomes has more binary digits. This increases the address space of the sine/cosine generator 65 as implemented in the ROM 15. Thus as the frequency control word increase in size linearly, the size of the ROM 15 must increase exponentially. To compensate for this, the prior art employs a method to minimize the size of the ROM 15 by exploiting the symmetrical nature of a sine wave and utilize mapping logic to synthesize a complete sine wave cycle from ¼ cycle of data from the phase accumulator 65. The phase-to-amplitude lookup table generates all the necessary data by reading forward then back through the lookup table.
“A 150-Mhz Direct Digital Frequency Synthesizer in 1.25 μM CMOS With −90-Dbc Spurious Performance, Nicholas, et al. IEEE Journal of Solid-State Circuits, December 1991 Volume: 26 Issue: 12, pp. 1959-1969, presents a monolithic CMOS direct digital frequency synthesizer (DDFS), which simultaneously achieves high spectral purity and wide bandwidth. The direct digital frequency synthesizer uses an efficient look-up table method for calculating the sine function and reduces ROM storage requirements by a factor of 128:1.
“A 100-Mhz, 16-B, Direct Digital Frequency Synthesizer with a 100-Dbc Spurious-Free Dynamic Range,” Madisetti, et al., IEEE Journal of Solid-State Circuits, August 1999, Volume: 34 Issue: 8, pp. 1034-1043, describes the architecture and implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm employing a technique similar to coordinate rotational digital computation (CORDIC). The architecture is implemented as a multiplierless, feedforward, and easily pipelineable datapath.
“Low-Power Direct Digital Frequency Synthesis for Wireless Communications,” Bellaouar, et al. IEEE Journal of Solid-State Circuits, March 2000, Volume: 35 Issue: 3, pp. 385-390 discusses a low-power direct digital frequency synthesizer (DDFS) architecture. It uses a smaller lookup table for sine and cosine functions compared to systems of the prior art with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points.
U.S. Pat. No. 5,999,581 (Bellaouar, et al.) describes a direct digital frequency synthesizer for generating a digital sine or cosine function waveform from a received digital input signal. A memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies the digital sample output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.
U.S. Pat. No. 5,986,483 (Yu, et al.) teaches a direct digital frequency synthesizer outputting a sine signal. The direct digital frequency synthesizer includes an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit. The accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M most-significant-bits of the symmetric sample address as the first M most-significant-bits of the sine signal. The fine circuit predicts the last N-M least-significant-bits of the sine signal from the last N-M least-significant-bits of the symmetric sample address according to the first M most-significant-bits of the symmetric sample address of the coarse circuit. Then, the sign circuit outputs a sign bit of the sine signal.
U.S. Pat. No. 5,737,253 (Madisetti, et al.) describes a direct digital frequency synthesizer with a phase accumulator provides a normalized angle θ to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. The sine/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations on a phasor on the unit circle whose x and y coordinates correspond to cosine and sine values.